In an electrical communication bus in which a memory controller is coupled with a memory device such as a GDDR3 DRAM memory, the DRAMs are designed to train their drive impedance and termination values against a reference resistor arrangement. However, process variations and resolution may cause variations in the final DRAM training values. The variations may occur within a memory controller coupled to the DRAM if it trains in a similar manner, thereby causing a mismatch in DRAM and controller impedances.
Such mismatches may cause timing offsets due to the reference voltages not being properly aligned to the resulting data eye. The problem may specifically occur in a GDDR3 interface for a memory controller to a GDDR3 memory device. However, the problem also occurs in a number of other system and subsystem electrical communication buses resulting in reduced timing margins.
Accordingly, what is needed is an arrangement which couples a memory device and its memory controller during memory driver training to reduce mismatches through calibration of a memory controller with a memory device driver.